1. Field of the Invention
The present invention relates to the design of integrated circuits. More specifically, the present invention relates to a method and an apparatus for determining gate-level delays in an integrated circuit.
2. Related Art
The process of designing integrated circuits often involves determining gate-level delays within the integrated circuit. These gate-level delays provide the designer with needed timing information to determine if the circuit meets timing requirements at clocked devices within the integrated circuit.
Currently available gate-level delay calculators avoid time-consuming transistor simulation by using pre-characterized libraries of delay and slew data for each gate. This data is pre-characterized for various values of input slew and lumped output capacitance for each gate timing waveform.
When gates are connected to detailed wire models instead of lumped output capacitances, a driver-model is derived from the library data in order to elicit the transistor behavior with the detailed wire model load. A common driver model for this purpose is either a voltage ramp in series with a resistor, or equivalently, a current ramp in parallel with a resistor. The resistor in these models is conventionally referred to as the “drive resistor.”
Refinements have been made to this type of model to account for complex aspects of transistor behavior, such as replacing the driver-model ramp with a more complicated time-domain waveform. Other approaches have tried multiple drive resistances and arbitrary dynamic impedances.
The problem with all of these approaches is a lack of sufficient generality; that is, they all assume some simplified behavioral model of the gate and work with a “best fit” to the actual behavior. In other words, each behavioral model includes some small set of parameters, which are set so that the transistor-level behavior is matched as closely as possible. The accuracy of these approaches depends explicitly on the choice of simplified behavior.
Unfortunately, as integrated circuit technology continues to advance to very deep submicron feature sizes, the transistor-level behavior can become very complicated, while at the same time faster circuit speeds require greater accuracy in delay calculations. Unfortunately, many existing approaches to calculating gate-level delay extend the behavioral complexity but do not offer guaranteed accuracy. Furthermore, as new transistor-level behaviors become increasingly more important, the behavioral complexity must be extended again and again. Consequently, as the number of model parameters grows so must the complexity of the characterization data.
Hence what is needed is a method and an apparatus for determining gate-level delays in an integrated circuit without the problems described above.